Layout Verification

Design rule checks and layout-versus-schematic comparisons run through an external engine selected by the engine argument: KLayout (DRC and LVS) or Calibre (DRC). KLayout 0.29.12 or newer is required; each check stops with an error naming an older version.

With engine="calibre", the rules file is an SVRF rule deck. Calibre runs a copy of it whose LAYOUT PATH, LAYOUT SYSTEM, LAYOUT PRIMARY (when the source is a component), DRC RESULTS DATABASE and DRC SUMMARY REPORT (when the deck declares one) name the files of the check; the deck itself is never edited. args holds Calibre’s command-line arguments, such as ("-hier", "-turbo", "4"). The Calibre engine requires a Photonic Canvas (PhotonForge Enterprise) license. Both engines return the same verification.DRCResults.

The LVS schematic can come from the component itself: with schematic unset or set to a Component, lvs_check() writes a SPICE schematic from Component.get_netlist(). Routes built by the parametric routing functions are written as wires and virtual connections as nets, so a routed component is its own design intent, and so is its unrouted version. pre_export_function adds the port markers and labels the rules file extracts pins from.

Functions

drc_check(source, rules, *[, engine, args, ...])

Run a design rule check (DRC) on a layout.

lvs_check(source, rules, *[, schematic, ...])

Run a layout-versus-schematic (LVS) comparison.

load_drc_results(path, *[, engine, ...])

Read the results database of an earlier design rule check.

load_lvs_results(path, *[, engine, ...])

Read the results database of an earlier layout-versus-schematic comparison.

DRC Results

Coordinates are in micrometers. DRCResults is also available as photonforge.DRCResults.

DRCResults(violations_by_category[, log, ...])

Results of a DRC run, from any engine.

DRCViolation(category, markers[, description])

The markers of one rule (category).

DRCCell(name[, variant, references])

A cell of the results.

DRCCellReference(parent, placement)

An example placement of a cell in another cell; parent is that cell's key.

Placement(x, y[, rotation, mirror, scale])

Magnification, then mirroring about x, then counter-clockwise rotation, then displacement.

DRCMarker(cell)

Marker of one violation, with the cell it was found in.

EdgeMarker(cell, edge)

One edge, for rules that report edges.

EdgePairMarker(cell, edge_pair[, symmetric])

Two edges; symmetric for same-layer rules (width, space), directed otherwise, and None when the engine does not record it (Calibre).

PolygonMarker(cell, hull[, holes])

A polygon with optional holes; boxes and paths are reported as polygons.

TextMarker(cell, text, position)

A text output and its position.

ValueMarker(cell, value)

Any other marker value, as the engine prints it (KLayout only).

Layout Pins

A photonic runset tells the ports of a passive cell apart only by layout labels, which the layout export does not write. layout_pins() returns a pre_export_function for lvs_check() that draws them on the layers the runset reads: devices get their core shapes as an outline, a box at each port and the port name; circuits get the names; routes nothing.

layout_pins(design, core_layer, *, ...[, ...])

Pre-export function that draws pins over Port.

LVS Results

LVSResults is also available as photonforge.LVSResults.

LVSResults(verdict, comparisons, layout, ...)

Results of a KLayout LVS run.

LVSComparison(circuit[, status, ...])

The comparison of a layout circuit with a schematic circuit.

LVSPair(kind, circuit[, status, ...])

Two objects KLayout paired; either side is None when it found no partner.

LVSMessage([severity, text, layout_circuit, ...])

A comparison or extraction message.

LVSGeometry(hull[, holes])

A polygon attached to a message.

LVSNetlist([circuits, device_classes, ...])

The layout or the schematic netlist; circuits is in file order, children first.

LVSCircuit(name[, boundary, nets, pins, ...])

A circuit of a netlist, with lookups by id or index that raise KeyError.

LVSNet(id[, name, connections, shapes, ...])

A net of a circuit, with its connections and, for the layout, its geometry per layer.

LVSConnection(kind[, pin, subcircuit, ...])

What a net connects to: a circuit pin, a subcircuit pin, or a device terminal.

LVSLabel(layer, text, position)

A text label KLayout attached to a layout net.

LVSPin(index[, name, net, properties])

A circuit pin and the net it connects to.

LVSDevice(id, device_class[, name, ...])

An extracted or schematic device; terminals maps terminal names to net ids.

LVSDevicePart(abstract, placement)

One of the extracted devices combined into a device.

LVSDeviceClass(name[, template, terminals, ...])

A device class; template names KLayout's built-in class it derives from.

LVSParameterDefinition(name, primary, default)

A parameter of a device class; primary parameters are compared by LVS.

LVSDeviceAbstract(name, device_class[, ...])

The geometry of an extracted device, per terminal and layer.

LVSSubcircuit(id, circuit[, name, ...])

An instance of another circuit; pins maps its pin indices to net ids.

LVSLayer(name[, source, connected_to, ...])

A layer of the extraction and the layers and global nets it connects to.