Technology¶
A typical fabrication process for microelectronics or photonics involves many layers of materials and processing steps to create active and passive devices. A process design kit (PDK) provided by the foundry describes this fabrication process, allowing us to convert 2D layout files to 3D representation of devices needed for electromagnetic simulations. In PhotonForge, this information is stored as a Technology object.
Loading a Technology¶
PhotonForge makes it really easy to load a technology and customize it. Each available PDK includes a technology function that can be called to create a Technology object with the desired specifications.
As an example, we will use the SiEPIC OpenEBL PDK through the siepic_forge module.
[1]:
import photonforge as pf
import siepic_forge as siepic
The technology function in the siepic_forge module is called ebeam, which defines the various layers, materials, thicknesses, and ports that we can use to build devices in this open-source platform.
If we want to, we can inspect the function to find out which parameters can be set:
[2]:
siepic.ebeam?
The default parameters represent the normal fabrication process for SiEPIC e-beam runs, but we can change those defaults if we want to test process variations.
We use the defaults to configure our project:
[3]:
pf.config.default_technology = siepic.ebeam()
That’s it! In 3 lines, we have loaded SiEPIC’s e-beam PDK and configured it to be the default technology in this PhotonForge project.
Note: PhotonForge supports a growing list of PDKs, and we are happy to assist you in creating your own custom technology if you require a specific process!
Technology Contents¶
Now that we have loaded the e-beam PDK, we can inspect this technology to find its definitions.
[4]:
pf.config.default_technology
[4]:
Name: SiEPIC EBeam Si
Version: 1.2.0
Layers
| Name | Layer | Description | Color | Pattern |
|---|---|---|---|---|
| Si | (1, 0) | SiEPIC - Waveguide | #ff80a818 | \\ |
| PinRec | (1, 10) | SiEPIC | #ff80a818 | xx |
| PinRecM | (1, 11) | SiEPIC | #80000018 | + |
| Si Slab | (2, 0) | Dedicated Run Layers - Device…… Layer Partial Etch | #c080ff18 | / |
| Direct Metal | (5, 0) | Dedicated Run Layers | #80a8ff18 | || |
| Oxide open to BOX | (6, 0) | Dedicated Run Layers | #ff000018 | - |
| Text | (10, 0) | Text-Not Fabricated | #00000018 | hollow |
| M1_heater | (11, 0) | TiW Heater | #0000ff18 | \\ |
| M2_router | (12, 0) | TiW/Au Routing Bilayer | #ffbf0018 | // |
| M_Open | (13, 0) | Bond Pad Open | #80005718 | \\ |
| Si n | (20, 0) | Dedicated Run Layers | #afff8018 | - |
| Si p | (21, 0) | Dedicated Run Layers | #ffd9df18 | = |
| Si n+ | (22, 0) | Dedicated Run Layers | #ff800018 | x |
| Si p+ | (23, 0) | Dedicated Run Layers | #ddff0018 | xx |
| Si n++ | (24, 0) | Dedicated Run Layers | #00ffff18 | + |
| Si p++ | (25, 0) | Dedicated Run Layers | #00800018 | ++ |
| ANT Reserved | (31, 0) | SiEPIC/ANT Reserved | #9580ff18 | / |
| ANT Reserved 1 | (33, 0) | ANT Reserved | #9580ff18 | / |
| Via to silicon | (40, 0) | Dedicated Run Layers | #0000ff18 | . |
| DevRec | (68, 0) | SiEPIC | #00800018 | . |
| FbrTgt | (81, 0) | SiEPIC/Dedicated Run Layers | #80808018 | ++ |
| ANT Reserved 2 | (102, 0) | ANT Reserved | #9580ff18 | / |
| ANT Reserved 3 | (110, 0) | ANT Reserved | #9580ff18 | / |
| Custom Dicing | (189, 0) | #00000018 | hollow | |
| SEM Imaging | (200, 0) | #ff000018 | x | |
| Deep Trench | (201, 0) | #00ff0018 | . | |
| Deep Trench Handling Exclusion | (202, 0) | #00760018 | : | |
| Thermal Isolation Trenches | (203, 0) | #00800018 | \ | |
| Laser Integration Shelf | (205, 0) | Dedicated Run Layers | #69ff0518 | xx |
| Floor Plan-Not Fabricated | (290, 0) | #c080ff18 | hollow | |
Error: device layer width is…… less than design rule | (301, 0) | DRC Errors | #80005718 | = |
Error: device layer spacing is…… less than design rule | (301, 1) | DRC Errors | #80005718 | - |
Warning: polygons/paths on…… PinRec layer (1/10) will NOT be fabricated | (301, 2) | DRC Errors | #80005718 | || |
Error: direct metal width is…… less than 5 microns | (305, 0) | DRC Errors | #80808018 | ++ |
Error: direct metal spacing is…… less than 10 microns | (305, 1) | DRC Errors | #80808018 | + |
Error: TiW width is less than 3…… microns | (311, 0) | DRC Errors | #ffa08018 | // |
Error: TiW spacing is less than…… 3 microns | (311, 1) | DRC Errors | #ffa08018 | / |
Error: Al width is less than…… design rule | (312, 0) | DRC Errors | #00ffff18 | | |
Error: Al spacing is less than…… design rule | (312, 1) | DRC Errors | #00ffff18 | // |
Error: Spacing between TiW and…… Al is less than 5 microns | (312, 3) | DRC Errors | #00ffff18 | \\ |
Error: Oxide window width is…… less than 10 microns | (313, 0) | DRC Errors | #01ff6b18 | || |
Error: Oxide window spacing is…… less than 10 microns | (313, 1) | DRC Errors | #01ff6b18 | | |
Error: Oxide window is not…… placed over Al | (313, 2) | DRC Errors | #01ff6b18 | // |
| Standard Design Area | (350, 0) | DRC Errors | #ddff0018 | \ |
Error: Features outside design…… area. Verify design size and centering. | (350, 1) | DRC Errors | #ddff0018 | : |
Error: Dicing lane width is…… less than 100 microns | (389, 0) | DRC Errors | #ff00ff18 | ++ |
Error: Spacing between dicing…… lane and devices is less than 50 microns | (389, 1) | DRC Errors | #ff00ff18 | + |
Error: SEM width is less than…… 500 nm | (400, 0) | DRC Errors | #ff9d9d18 | x |
| Deep Trench Design Area | (401, 0) | DRC Errors | #80a8ff18 | xx |
Error: Metal, SEM, or handling…… region overlap with deep trenches. Verify design centering | (401, 1) | DRC Errors | #80a8ff18 | x |
Warning: Silicon features…… outside deep trench design area. Verify accuracy before submission | (401, 2) | DRC Errors | #80a8ff18 | = |
Error: Spacing between metal…… and deep trench is less than 30 microns | (401, 3) | DRC Errors | #80a8ff18 | - |
Error: Deep trench width is…… less than 260 microns | (401, 4) | DRC Errors | #80a8ff18 | || |
Error: Deep trench handling…… area missing. Please add handling area of size shown by polygons | (402, 0) | DRC Errors | #ff000018 | + |
Error: Features inside deep…… trench handling area | (402, 1) | DRC Errors | #ff000018 | xx |
Error: Thermal isolation width…… is less than design rule | (403, 0) | DRC Errors | #50008018 | ++ |
Error: Thermal isolation…… spacing is less than design rule | (403, 1) | DRC Errors | #50008018 | + |
Error: Spacing between thermal…… isolation and metal is less than design rule | (403, 2) | DRC Errors | #50008018 | xx |
Error: Thermal isolation and…… device layer overlap, or spacing is less than design rule | (403, 3) | DRC Errors | #50008018 | x |
Dream Photonics Black Box-Not…… Fabricated | (998, 0) | #00000018 | hollow | |
| Errors | (999, 0) | SiEPIC | #0000ff18 | || |
Extrusion Specs
| # | Mask | Limits (μm) | Sidewal (°) | Opt. Medium | Elec. Medium |
|---|---|---|---|---|---|
| 0 | () | -inf, 0 | 0 | cSi_Li1993_293K | Si |
| 1 | () | -2, 2.5 | 0 | SiO2_Palik_Lossless | SiO2 |
| 2 | 'M1_heater'**0.3 | 2.2, 2.7 | 0 | SiO2_Palik_Lossless | SiO2 |
| 3 | 'M2_router'**0.3 | 2.2, 3.3 | 0 | SiO2_Palik_Lossless | SiO2 |
| 4 | 'M1_heater' | 2.2, 2.4 | 0 | W_Werner2009 | LossyMetalMedium……(frequency_range=(100000000.0, 200000000000.0), conductivity=1.6, fit_param={'max_num_poles': 16}) |
| 5 | 'M2_router' | 2.4, 3 | 0 | Au_Olmon2012evaporated | LossyMetalMedium……(frequency_range=(100000000.0, 200000000000.0), conductivity=17.0, fit_param={'max_num_poles': 16}) |
| 6 | 'M_Open' | 3, 3.3 | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
| 7 | 'Oxide open to BOX' | 0, inf | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
| 8 | 'Si' | 0, 0.22 | 0 | cSi_Li1993_293K | Si |
| 9 | 'Si Slab' | 0, 0.09 | 0 | cSi_Li1993_293K | Si |
| 10 | 'Deep Trench' +…… 'Thermal Isolation Trenches' | -inf, inf | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
Ports
| Name | Classification | Description | Width (μm) | Limits (μm) | Radius (μm) | Modes | Target n_eff | Path profiles (μm) | Voltage path | Current path |
|---|---|---|---|---|---|---|---|---|---|---|
| MM_TE_1550_2000 | optical | Multimode Strip TE 1550 nm,…… w=2000 nm | 6 | -2, 2.22 | 0 | 10 | 3.5 | 'Si': 2 | ||
| MM_TE_1550_3000 | optical | Multimode Strip TE 1550 nm,…… w=3000 nm | 6 | -2, 2.22 | 0 | 15 | 3.5 | 'Si': 3 | ||
| Rib_TE_1310_350 | optical | Rib (90 nm slab) TE 1310 nm,…… w=350 nm | 2.35 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35, 'Si…… Slab': 3 | ||
| Rib_TE_1550_500 | optical | Rib (90 nm slab) TE 1550 nm,…… w=500 nm | 2.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5, 'Si…… Slab': 3 | ||
| Slot_TE_1550_500 | optical | Slot TE 1550 nm, w=500 nm,…… gap=100nm | 3 | -1, 1.22 | 0 | 1 | 3.5 | 'Si': 0.2 (-0.15),…… 'Si': 0.2 (+0.15) | ||
| TE-TM_1550_450 | optical | Strip TE-TM 1550, w=450 nm | 2.2 | -1, 1.22 | 0 | 2 | 3.5 | 'Si': 0.45 | ||
| TE_1310_350 | optical | Strip TE 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35 | ||
| TE_1310_410 | optical | Strip TE 1310 nm, w=410 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.41 | ||
| TE_1550_500 | optical | Strip TE 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5 | ||
| TM_1310_350 | optical | Strip TM 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.35 | ||
| TM_1550_500 | optical | Strip TM 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.5 | ||
| eskid_TE_1550 | optical | eskid TE 1550 | 2 | -0.7, 0.92 | 0 | 1 | 3.5 | 'Si': 0.35,…… 'Si': 0.06 (+0.265), 'Si': 0.06 (-0.265), 'Si': 0.06 (+0.385), 'Si': 0.06 (-0.385), 'Si': 0.06 (+0.505), 'Si': 0.06 (-0.505), 'Si': 0.06 (+0.625), 'Si': 0.06 (-0.625) |
Background medium
- Optical: Medium(permittivity=1.0)
- Electrical: Medium(permittivity=1.0)
Connections: []
Besides a name and version, all technologies contain 5 main attributes:
background_medium: Tidy3D medium used as default background material for the extruded 3D device.
layers: dictionary of layer specifications that contain all layers available in the PDK.
extrusion_specs: list of extrusion specifications that describe how the geometries from each layer are combined and extruded to generate the 3D device.
ports: dictionary of port specifications describing the ports (waveguide profiles) used by default within the PDK.
connections: List of pairs of layers that are considered electrically connected in the technology stack (e.g. a metal layer and its access via).
In most cases, the layer and port dictionaries are the most used when creating components. These are the layers defined in the SiEPIC e-beam PDK:
[5]:
pf.config.default_technology.layers
[5]:
| Name | Layer | Description | Color | Pattern |
|---|---|---|---|---|
| Si | (1, 0) | SiEPIC - Waveguide | #ff80a818 | \\ |
| PinRec | (1, 10) | SiEPIC | #ff80a818 | xx |
| PinRecM | (1, 11) | SiEPIC | #80000018 | + |
| Si Slab | (2, 0) | Dedicated Run Layers - Device…… Layer Partial Etch | #c080ff18 | / |
| Direct Metal | (5, 0) | Dedicated Run Layers | #80a8ff18 | || |
| Oxide open to BOX | (6, 0) | Dedicated Run Layers | #ff000018 | - |
| Text | (10, 0) | Text-Not Fabricated | #00000018 | hollow |
| M1_heater | (11, 0) | TiW Heater | #0000ff18 | \\ |
| M2_router | (12, 0) | TiW/Au Routing Bilayer | #ffbf0018 | // |
| M_Open | (13, 0) | Bond Pad Open | #80005718 | \\ |
| Si n | (20, 0) | Dedicated Run Layers | #afff8018 | - |
| Si p | (21, 0) | Dedicated Run Layers | #ffd9df18 | = |
| Si n+ | (22, 0) | Dedicated Run Layers | #ff800018 | x |
| Si p+ | (23, 0) | Dedicated Run Layers | #ddff0018 | xx |
| Si n++ | (24, 0) | Dedicated Run Layers | #00ffff18 | + |
| Si p++ | (25, 0) | Dedicated Run Layers | #00800018 | ++ |
| ANT Reserved | (31, 0) | SiEPIC/ANT Reserved | #9580ff18 | / |
| ANT Reserved 1 | (33, 0) | ANT Reserved | #9580ff18 | / |
| Via to silicon | (40, 0) | Dedicated Run Layers | #0000ff18 | . |
| DevRec | (68, 0) | SiEPIC | #00800018 | . |
| FbrTgt | (81, 0) | SiEPIC/Dedicated Run Layers | #80808018 | ++ |
| ANT Reserved 2 | (102, 0) | ANT Reserved | #9580ff18 | / |
| ANT Reserved 3 | (110, 0) | ANT Reserved | #9580ff18 | / |
| Custom Dicing | (189, 0) | #00000018 | hollow | |
| SEM Imaging | (200, 0) | #ff000018 | x | |
| Deep Trench | (201, 0) | #00ff0018 | . | |
| Deep Trench Handling Exclusion | (202, 0) | #00760018 | : | |
| Thermal Isolation Trenches | (203, 0) | #00800018 | \ | |
| Laser Integration Shelf | (205, 0) | Dedicated Run Layers | #69ff0518 | xx |
| Floor Plan-Not Fabricated | (290, 0) | #c080ff18 | hollow | |
Error: device layer width is…… less than design rule | (301, 0) | DRC Errors | #80005718 | = |
Error: device layer spacing is…… less than design rule | (301, 1) | DRC Errors | #80005718 | - |
Warning: polygons/paths on…… PinRec layer (1/10) will NOT be fabricated | (301, 2) | DRC Errors | #80005718 | || |
Error: direct metal width is…… less than 5 microns | (305, 0) | DRC Errors | #80808018 | ++ |
Error: direct metal spacing is…… less than 10 microns | (305, 1) | DRC Errors | #80808018 | + |
Error: TiW width is less than 3…… microns | (311, 0) | DRC Errors | #ffa08018 | // |
Error: TiW spacing is less than…… 3 microns | (311, 1) | DRC Errors | #ffa08018 | / |
Error: Al width is less than…… design rule | (312, 0) | DRC Errors | #00ffff18 | | |
Error: Al spacing is less than…… design rule | (312, 1) | DRC Errors | #00ffff18 | // |
Error: Spacing between TiW and…… Al is less than 5 microns | (312, 3) | DRC Errors | #00ffff18 | \\ |
Error: Oxide window width is…… less than 10 microns | (313, 0) | DRC Errors | #01ff6b18 | || |
Error: Oxide window spacing is…… less than 10 microns | (313, 1) | DRC Errors | #01ff6b18 | | |
Error: Oxide window is not…… placed over Al | (313, 2) | DRC Errors | #01ff6b18 | // |
| Standard Design Area | (350, 0) | DRC Errors | #ddff0018 | \ |
Error: Features outside design…… area. Verify design size and centering. | (350, 1) | DRC Errors | #ddff0018 | : |
Error: Dicing lane width is…… less than 100 microns | (389, 0) | DRC Errors | #ff00ff18 | ++ |
Error: Spacing between dicing…… lane and devices is less than 50 microns | (389, 1) | DRC Errors | #ff00ff18 | + |
Error: SEM width is less than…… 500 nm | (400, 0) | DRC Errors | #ff9d9d18 | x |
| Deep Trench Design Area | (401, 0) | DRC Errors | #80a8ff18 | xx |
Error: Metal, SEM, or handling…… region overlap with deep trenches. Verify design centering | (401, 1) | DRC Errors | #80a8ff18 | x |
Warning: Silicon features…… outside deep trench design area. Verify accuracy before submission | (401, 2) | DRC Errors | #80a8ff18 | = |
Error: Spacing between metal…… and deep trench is less than 30 microns | (401, 3) | DRC Errors | #80a8ff18 | - |
Error: Deep trench width is…… less than 260 microns | (401, 4) | DRC Errors | #80a8ff18 | || |
Error: Deep trench handling…… area missing. Please add handling area of size shown by polygons | (402, 0) | DRC Errors | #ff000018 | + |
Error: Features inside deep…… trench handling area | (402, 1) | DRC Errors | #ff000018 | xx |
Error: Thermal isolation width…… is less than design rule | (403, 0) | DRC Errors | #50008018 | ++ |
Error: Thermal isolation…… spacing is less than design rule | (403, 1) | DRC Errors | #50008018 | + |
Error: Spacing between thermal…… isolation and metal is less than design rule | (403, 2) | DRC Errors | #50008018 | xx |
Error: Thermal isolation and…… device layer overlap, or spacing is less than design rule | (403, 3) | DRC Errors | #50008018 | x |
Dream Photonics Black Box-Not…… Fabricated | (998, 0) | #00000018 | hollow | |
| Errors | (999, 0) | SiEPIC | #0000ff18 | || |
Any place where a layer must be specified will accept a layer name instead of the layer tuple and use this dictionary to match the name. More information about layers can be found in the layers guide.
Similarly, we can take a look at the available ports:
[6]:
pf.config.default_technology.ports
[6]:
| Name | Classification | Description | Width (μm) | Limits (μm) | Radius (μm) | Modes | Target n_eff | Path profiles (μm) | Voltage path | Current path |
|---|---|---|---|---|---|---|---|---|---|---|
| MM_TE_1550_2000 | optical | Multimode Strip TE 1550 nm,…… w=2000 nm | 6 | -2, 2.22 | 0 | 10 | 3.5 | 'Si': 2 | ||
| MM_TE_1550_3000 | optical | Multimode Strip TE 1550 nm,…… w=3000 nm | 6 | -2, 2.22 | 0 | 15 | 3.5 | 'Si': 3 | ||
| Rib_TE_1310_350 | optical | Rib (90 nm slab) TE 1310 nm,…… w=350 nm | 2.35 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35, 'Si…… Slab': 3 | ||
| Rib_TE_1550_500 | optical | Rib (90 nm slab) TE 1550 nm,…… w=500 nm | 2.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5, 'Si…… Slab': 3 | ||
| Slot_TE_1550_500 | optical | Slot TE 1550 nm, w=500 nm,…… gap=100nm | 3 | -1, 1.22 | 0 | 1 | 3.5 | 'Si': 0.2 (-0.15),…… 'Si': 0.2 (+0.15) | ||
| TE-TM_1550_450 | optical | Strip TE-TM 1550, w=450 nm | 2.2 | -1, 1.22 | 0 | 2 | 3.5 | 'Si': 0.45 | ||
| TE_1310_350 | optical | Strip TE 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35 | ||
| TE_1310_410 | optical | Strip TE 1310 nm, w=410 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.41 | ||
| TE_1550_500 | optical | Strip TE 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5 | ||
| TM_1310_350 | optical | Strip TM 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.35 | ||
| TM_1550_500 | optical | Strip TM 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.5 | ||
| eskid_TE_1550 | optical | eskid TE 1550 | 2 | -0.7, 0.92 | 0 | 1 | 3.5 | 'Si': 0.35,…… 'Si': 0.06 (+0.265), 'Si': 0.06 (-0.265), 'Si': 0.06 (+0.385), 'Si': 0.06 (-0.385), 'Si': 0.06 (+0.505), 'Si': 0.06 (-0.505), 'Si': 0.06 (+0.625), 'Si': 0.06 (-0.625) |
If required, new port specifications can also be included to allow us to work with custom waveguide interconnections.