IntegralTimeStepper¶
- class photonforge.IntegralTimeStepper(*, scale=, start_value=0.0, limits=(None, None), output_port=None, reset_port=None, reset_trigger="rise", reset_tolerance=0.0)[source]¶
Time stepper for integrating electrical signals in time.
\[y_k = y_{k - 1} + s x_k \Delta t\]- Parameters:
scale (Annotated[float, units='s⁻¹']) – Input scaling factor \(s\).
start_value (Annotated[float, units='√W']) – Starting output value after reset.
limits (Annotated[Sequence[Annotated[float, units='√W'] | None], maxItems=2, minItems=2]) – Output value limits.
output_port (str | None) – Name of the port used as output. If
None, the last port is used (in the sorted list of ports).reset_port (str | None) – Name of the port used as reset signal. If
None, the reset feature is disabled.reset_trigger (Literal['fall', 'rise', 'both']) – Type of edge used for triggering a reset.
reset_tolerance (float) – Value change tolerance for triggering a reset.
Methods
bind_native(step, keys[, state, cstate, context])Bind a compiled step function.
reset()Reset any internal state of the time stepper.
setup(component, time_step, *[, ...])Initialize the time stepper.
setup_state(*, time_step, component, **kwargs)Initialize internal state.
step([inputs, steps, time_step, show_progress])Compute the outputs of this time stepper, given inputs.
step_single(inputs, outputs, time_index, ...)Take a single time step on the given inputs.
update(*args, **kwargs)Update this time stepper.
write_verilog_a(path, *[, backend, ...])Write this configured time stepper as one Verilog-A module.
Attributes
parametric_functionFunction used to update the time stepper.
parametric_kwargsKeyword arguments used to update the time stepper.
path_delaysMinimum delay in time steps of each (input key, output key) signal path; missing pairs have no path and None means every input reaches every output within the time step.
propertiesObject properties.
random_variablesRandom variables associated to the time stepper's parameters.