lvs_check

photonforge.lvs_check(source, rules, *, schematic=None, engine=None, args=None, variable_names=None, results_file=None, load_shapes=True, timeout=None, pre_export_function=None, show_progress=True)

Run a layout-versus-schematic (LVS) comparison.

The engine runs the rules file with the layout, schematic and results paths as script variables. For KLayout, the rules file is an LVS runset (.lvs or .lylvs) that calls source($gdsfile), schematic($schematicfile), report_lvs($resultsfile) and compare. The results database is then read with KLayout’s own Python module, so the executable must include Python, as the official builds do.

Parameters:

  • source (Component | str | PathLike) – Component to check, exported to GDSII with default settings, or path to a GDSII or OASIS file.

  • rules (str | PathLike) – Rules file for the engine.

  • schematic (Component | str | PathLike | None) – Design intent. A component is written as a SPICE schematic from its netlist (see note); None uses source, which must then be a component. A path is a netlist in a format the rules file reads, usually SPICE.

  • engine (str | None) – Verification engine, "klayout" (Calibre runs DRC only). None uses config.default_drc_lvs_engine, unless it names Calibre, and otherwise the first engine found.

  • args (dict[str, object] | None) – Extra script variables for the rules file, passed as -rd name=value with str(value).

  • variable_names (dict[str, str] | None) – Names of the file variables used by the rules file when they differ from the defaults. Keys are "gdsfile", "schematicfile" and "resultsfile".

  • results_file (str | PathLike | None) – Keep the engine’s native results database (.lvsdb) at this path.

  • load_shapes (bool) – Include the layout geometry of each net.

  • timeout (float | None) – Seconds allowed for each engine run; TimeoutError when one exceeds it.

  • pre_export_function (Callable[[Component], object] | None) – Called with a shallow copy of each component exported from source or written for schematic, as in write_layout(). Use it to add the port markers and labels the rules file extracts pins from; verification.layout_pins() can be used as an example.

  • show_progress (bool) – Show the phase and the elapsed time while the engine runs.

Returns:

Verdict, circuit comparisons, and both netlists. Rules files that exit with a non-zero code on a mismatch do not raise once compare ran; the code is in LVSResults.exit_code. A runset that stops before compare writes no results and raises.

Return type:

photonforge.verification.LVSResults

Note

A schematic written from a component has one subcircuit per cell, named as in the exported layout, whose pins are its planar ports, then its terminals; fiber and Gaussian ports have no layout. Each instance with pins is the line X<i>, where i is its index in Component.get_netlist(), and the results carry its placement. Connections, butt couplings, virtual connections, terminal nets and virtual nets become nets. A route built by photonforge.parametric (route, route_auto and the other route_* functions) is a wire: its ports are one net, and neither it nor its sections are written, so a routed component is its own design intent. Port terminals and mode counts are not represented.

The executable is taken from config.klayout_executable when set, then searched in PATH and in common install locations.