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PhotonForge
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  • Getting Started
  • Quick Start
  • Short Guides
    • Technology
    • Layers
    • Ports
    • Electrical Ports
    • Fiber Ports
    • PDK Components
    • Parametric Component Library
    • Custom Technology
    • Custom Parametric Components
    • Routing and Connections
    • Importing a GDSII/OASIS Layout
    • Exporting a GDSII/OASIS Layout
    • S Parameters
    • Tidy3D Model
    • Circuit Model
    • Data Model
    • Custom Model
    • Layout vs. Schematic (LVS)
    • Layout Examples
      • Components
      • Instances and References
      • Paths, Routes, and Transitions
      • Grid Snapping
      • Grid and Pack
      • KLayout DRC Plugin
    • Compact Models
      • Analytic Directional Coupler Model
      • Analytic Waveguide Model
      • Analytic MZI Model
  • Examples
    • Component design
      • Y Splitter
      • Mach-Zehnder Interferometer
      • Waveguide Crossing
      • 90° Optical Hybrid
      • Cascaded MZI Filter
      • Cascaded Rings Filter
      • Polarization Splitter Rotator
      • Grating Coupler
      • Inverse Designed Grating Coupler
      • Edge Coupler
      • MMI Optimization with Tidy3D Design Plugin
      • Waveguide Coupling Simulation with Port Bending
      • Spiral Waveguide
      • Time-Domain Simulation of a Mach–Zehnder Interferometer
      • Polarizing Beam Splitter
      • Fabrication-Aware Simulation: Two Coupled Ring Resonator Filter
      • Bandstructure Analysis of 1D Periodic Waveguides
    • Active device design
      • Tunable MZI
      • Electro-Optic Mach-Zehnder Modulator
      • Signal Integrity Analysis of a 100 Gbps Transmitter
      • Folded Electro-Optic Modulators on TFLN: Analysis
      • Programmable Photonic Circuit
      • BTO Electro-Optic Modulator
      • Switch Array
      • Time-Domain Simulation of a Low-Pass Filter
      • Differential Coplanar Waveguide
      • Four-Channel WDM Filter
      • Time-Domain Simulation of a Mach–Zehnder Modulator (Toy Model)
      • Time-Domain Simulation of a Mach–Zehnder Modulator
      • Self Pulsing in Silicon Microring Resonator
      • Two-Segment Silicon Microring Modulator
      • 3D doping extrusion from a 2D carrier profile
      • Noise Under Large-Signal Modulation
    • Full chip layout
      • Add-Drop Filter Layout
      • Building Circuit Models from Layout Files
      • Microring Modulator
      • Dual Polarization IQ Modulator
      • Quantum Chip
      • LIDAR
      • Foundry-Compatible PIC Design Flow
      • Folded Electro-Optic Modulators on TFLN: Layout
    • Chip Design Tutorials
      • Data Communication
        • Technology and PDK Setup
        • Custom Component Library
        • Chip Layout
        • Design Rule Check
        • Chip Simulation
      • Quantum
        • Custom Component Library
        • Quantum Chip Layout
        • Quantum Chip Simulation
  • Python API Reference
    • Module Configuration
    • Structures
      • Circle
      • Path
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      • ConstructiveSolid
      • Extruded
      • Polyhedron
      • boolean
      • envelope
      • heal
      • offset
      • text
      • tidy3d_structures_from_layout
    • Stencils
      • apodized_focused_grating
      • apodized_grating
      • cross
      • focused_grating
      • grating
      • linear_taper
      • mmi
      • ruler
      • vernier_scale
      • as_component
    • Components
      • Component
      • FiberPort
      • GaussianPort
      • Label
      • PhfStream
      • Port
      • Reference
      • Terminal
      • component_from_netlist
      • find_top_level
      • load_layout
      • load_phf
      • parametric_component
      • set_unique_names
      • write_layout
      • write_phf
    • Parametric Components
      • bend
      • crossing
      • crossing45
      • dual_ring_coupler
      • rectangular_spiral
      • circular_spiral
      • ring_coupler
      • s_bend
      • s_bend_coupler
      • s_bend_ring_coupler
      • s_bend_straight_coupler
      • straight
      • transition
      • route
      • route_taper
      • route_manhattan
      • route_s_bend
      • route_length
    • Technology
      • ExtrusionSpec
      • LayerSpec
      • MaskSpec
      • PortSpec
      • Technology
      • basic_technology
      • cpw_spec
      • virtual_port_spec
      • parametric_technology
      • port_modes
    • Models
      • Model
      • AnalyticDirectionalCouplerModel
      • AnalyticMZIModel
      • AnalyticWaveguideModel
      • CircuitModel
      • CrossingModel
      • DataModel
      • DirectionalCouplerModel
      • DirectionalCouplerCircuitModel
      • EMEModel
      • PolarizationBeamSplitterModel
      • PolarizationSplitterRotatorModel
      • PowerSplitterModel
      • TerminationModel
      • Tidy3DModel
      • TwoPortModel
      • WaveguideModel
      • TimeStepper
      • AnalyticWaveguideTimeStepper
      • CWLaserTimeStepper
      • CircuitTimeStepper
      • DMLaserTimeStepper
      • DelayedTimeStepper
      • DifferentialTimeStepper
      • ElectricalAmplifierTimeStepper
      • ExpressionTimeStepper
      • FilterTimeStepper
      • IntegralTimeStepper
      • OpticalAmplifierTimeStepper
      • OpticalNoiseTimeStepper
      • OpticalPulseTimeStepper
      • PhaseModTimeStepper
      • PhotodiodeTimeStepper
      • SMatrixTimeStepper
      • TerminatedModTimeStepper
      • WaveformTimeStepper
      • PoleResidueMatrix
      • SMatrix
      • TimeDomainModel
      • TimeSeries
      • abort_pending_tasks
      • frequency_classification
      • load_snp
      • pole_residue_fit
      • register_model_class
      • register_time_stepper_class
      • cache_s_matrix
      • cache_capacity
      • clear_cache
    • Monte Carlo
      • RandomVariable
      • s_matrix
    • Utilities
      • Expression
      • Interpolator
      • Properties
      • LayerTable
      • ExtrusionTable
      • PortSpecTable
      • LiveViewer
      • grid_layout
      • pack_layout
      • s_bend_length
      • grid_ceil
      • grid_floor
      • snap_to_grid
      • plot_s_matrix
      • tidy3d_plot
    • Typing
      • annotate
      • kwargs_for
      • array
      • expression
  • Frequently Asked Questions
  • Change Log
  • Software License Agreement
  • Third-Party Licenses
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Data Communication¶

Technology and PDK Setup
Custom Component Library
Chip Layout
Design Rule Check
Chip Simulation
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