FitRecord

class photonforge.spice.FitRecord(component_name, instance_indices, module_name, va_path, artifact_path, fit_mode, rms_error, rms_no_delays, rms_auto_delays, accepted, rejection_reasons, fit_options, passivity_policy, sampled_is_passive, model_is_passive, model_is_stable, n_poles, delays, fit_cache_key, va_cache_key, compiled_cache_key)[source]

Record of the pole-residue conversion for one unique leaf.

Parameters:

  • component_name (str) – Name identifying the transformed leaf component.

  • instance_indices (tuple[int, ...]) – Flattened instance indices sharing this model.

  • module_name (str) – Generated Verilog-A module name.

  • va_path (Path) – Path to the cached Verilog-A source.

  • artifact_path (Path | None) – Compiled simulator artifact path, or None when no artifact was produced.

  • fit_mode (str) – Selected candidate, "no-delays" or "auto-delays".

  • rms_error (float) – RMS error of the selected fit.

  • rms_no_delays (float) – RMS error of the no-delay candidate, or infinity when that candidate is unavailable.

  • rms_auto_delays (float) – RMS error of the automatic-delay candidate, or infinity when that candidate is unavailable.

  • accepted (bool) – Whether the selected candidate met the RMS tolerance and backend constraints.

  • rejection_reasons (dict[str, str]) – Rejection reason indexed by candidate mode.

  • fit_options (dict[str, Any]) – Common fitting options recorded for both candidates, including the resolved real/passive request, target z0, and source impedances.

  • passivity_policy (str) – Requested passivity policy.

  • sampled_is_passive (bool) – Whether the sampled S-data is passive.

  • model_is_passive (bool) – Whether the selected model is actually passive.

  • model_is_stable (bool) – Whether every selected pole is strictly stable.

  • n_poles (int) – Number of poles in the selected model.

  • delays (dict[tuple[str, str], float]) – Selected matrix-element delays in seconds, keyed by input and output channel.

  • fit_cache_key (str) – Content-addressed key for sampled data and fit options.

  • va_cache_key (str) – Content-addressed key for the Verilog-A source.

  • compiled_cache_key (str | None) – Cache key for the compiled artifact, or None when compilation did not produce one.

Attributes

component_name

instance_indices

module_name

va_path

artifact_path

fit_mode

rms_error

rms_no_delays

rms_auto_delays

accepted

rejection_reasons

fit_options

passivity_policy

sampled_is_passive

model_is_passive

model_is_stable

n_poles

delays

fit_cache_key

va_cache_key

compiled_cache_key