Quick Start¶
In this quick start, we will show you how to:
Load a foundry Process Design Kit (PDK) in PhotonForge
Load PDK components
Run FDTD simulation by converting 2D layout files to 3D for electromagnetic simulations in a single line of code
Step 1: Loading a Foundry PDK¶
Start by importing numpy, photonforge, and siepic pdk library
[1]:
import numpy as np
import photonforge as pf
import siepic_forge as siepic_pdk
Select the open source ebeam process node, also called the technology stack
[2]:
# load the technology and set is as the default
technology = siepic_pdk.ebeam()
pf.config.default_technology = technology
[3]:
technology
[3]:
Name: SiEPIC EBeam Si
Version: 1.2.0
Layers
| Name | Layer | Description | Color | Pattern |
|---|---|---|---|---|
| Si | (1, 0) | SiEPIC - Waveguide | #ff80a818 | \\ |
| PinRec | (1, 10) | SiEPIC | #ff80a818 | xx |
| PinRecM | (1, 11) | SiEPIC | #80000018 | + |
| Si Slab | (2, 0) | Dedicated Run Layers - Device…… Layer Partial Etch | #c080ff18 | / |
| Direct Metal | (5, 0) | Dedicated Run Layers | #80a8ff18 | || |
| Oxide open to BOX | (6, 0) | Dedicated Run Layers | #ff000018 | - |
| Text | (10, 0) | Text-Not Fabricated | #00000018 | hollow |
| M1_heater | (11, 0) | TiW Heater | #0000ff18 | \\ |
| M2_router | (12, 0) | TiW/Au Routing Bilayer | #ffbf0018 | // |
| M_Open | (13, 0) | Bond Pad Open | #80005718 | \\ |
| Si n | (20, 0) | Dedicated Run Layers | #afff8018 | - |
| Si p | (21, 0) | Dedicated Run Layers | #ffd9df18 | = |
| Si n+ | (22, 0) | Dedicated Run Layers | #ff800018 | x |
| Si p+ | (23, 0) | Dedicated Run Layers | #ddff0018 | xx |
| Si n++ | (24, 0) | Dedicated Run Layers | #00ffff18 | + |
| Si p++ | (25, 0) | Dedicated Run Layers | #00800018 | ++ |
| ANT Reserved | (31, 0) | SiEPIC/ANT Reserved | #9580ff18 | / |
| ANT Reserved 1 | (33, 0) | ANT Reserved | #9580ff18 | / |
| Via to silicon | (40, 0) | Dedicated Run Layers | #0000ff18 | . |
| DevRec | (68, 0) | SiEPIC | #00800018 | . |
| FbrTgt | (81, 0) | SiEPIC/Dedicated Run Layers | #80808018 | ++ |
| ANT Reserved 2 | (102, 0) | ANT Reserved | #9580ff18 | / |
| ANT Reserved 3 | (110, 0) | ANT Reserved | #9580ff18 | / |
| Custom Dicing | (189, 0) | #00000018 | hollow | |
| SEM Imaging | (200, 0) | #ff000018 | x | |
| Deep Trench | (201, 0) | #00ff0018 | . | |
| Deep Trench Handling Exclusion | (202, 0) | #00760018 | : | |
| Thermal Isolation Trenches | (203, 0) | #00800018 | \ | |
| Laser Integration Shelf | (205, 0) | Dedicated Run Layers | #69ff0518 | xx |
| Floor Plan-Not Fabricated | (290, 0) | #c080ff18 | hollow | |
Error: device layer width is…… less than design rule | (301, 0) | DRC Errors | #80005718 | = |
Error: device layer spacing is…… less than design rule | (301, 1) | DRC Errors | #80005718 | - |
Warning: polygons/paths on…… PinRec layer (1/10) will NOT be fabricated | (301, 2) | DRC Errors | #80005718 | || |
Error: direct metal width is…… less than 5 microns | (305, 0) | DRC Errors | #80808018 | ++ |
Error: direct metal spacing is…… less than 10 microns | (305, 1) | DRC Errors | #80808018 | + |
Error: TiW width is less than 3…… microns | (311, 0) | DRC Errors | #ffa08018 | // |
Error: TiW spacing is less than…… 3 microns | (311, 1) | DRC Errors | #ffa08018 | / |
Error: Al width is less than…… design rule | (312, 0) | DRC Errors | #00ffff18 | | |
Error: Al spacing is less than…… design rule | (312, 1) | DRC Errors | #00ffff18 | // |
Error: Spacing between TiW and…… Al is less than 5 microns | (312, 3) | DRC Errors | #00ffff18 | \\ |
Error: Oxide window width is…… less than 10 microns | (313, 0) | DRC Errors | #01ff6b18 | || |
Error: Oxide window spacing is…… less than 10 microns | (313, 1) | DRC Errors | #01ff6b18 | | |
Error: Oxide window is not…… placed over Al | (313, 2) | DRC Errors | #01ff6b18 | // |
| Standard Design Area | (350, 0) | DRC Errors | #ddff0018 | \ |
Error: Features outside design…… area. Verify design size and centering. | (350, 1) | DRC Errors | #ddff0018 | : |
Error: Dicing lane width is…… less than 100 microns | (389, 0) | DRC Errors | #ff00ff18 | ++ |
Error: Spacing between dicing…… lane and devices is less than 50 microns | (389, 1) | DRC Errors | #ff00ff18 | + |
Error: SEM width is less than…… 500 nm | (400, 0) | DRC Errors | #ff9d9d18 | x |
| Deep Trench Design Area | (401, 0) | DRC Errors | #80a8ff18 | xx |
Error: Metal, SEM, or handling…… region overlap with deep trenches. Verify design centering | (401, 1) | DRC Errors | #80a8ff18 | x |
Warning: Silicon features…… outside deep trench design area. Verify accuracy before submission | (401, 2) | DRC Errors | #80a8ff18 | = |
Error: Spacing between metal…… and deep trench is less than 30 microns | (401, 3) | DRC Errors | #80a8ff18 | - |
Error: Deep trench width is…… less than 260 microns | (401, 4) | DRC Errors | #80a8ff18 | || |
Error: Deep trench handling…… area missing. Please add handling area of size shown by polygons | (402, 0) | DRC Errors | #ff000018 | + |
Error: Features inside deep…… trench handling area | (402, 1) | DRC Errors | #ff000018 | xx |
Error: Thermal isolation width…… is less than design rule | (403, 0) | DRC Errors | #50008018 | ++ |
Error: Thermal isolation…… spacing is less than design rule | (403, 1) | DRC Errors | #50008018 | + |
Error: Spacing between thermal…… isolation and metal is less than design rule | (403, 2) | DRC Errors | #50008018 | xx |
Error: Thermal isolation and…… device layer overlap, or spacing is less than design rule | (403, 3) | DRC Errors | #50008018 | x |
Dream Photonics Black Box-Not…… Fabricated | (998, 0) | #00000018 | hollow | |
| Errors | (999, 0) | SiEPIC | #0000ff18 | || |
Extrusion Specs
| # | Mask | Limits (μm) | Sidewal (°) | Opt. Medium | Elec. Medium |
|---|---|---|---|---|---|
| 0 | () | -inf, 0 | 0 | cSi_Li1993_293K | Si |
| 1 | () | -2, 2.5 | 0 | SiO2_Palik_Lossless | SiO2 |
| 2 | 'M1_heater'**0.3 | 2.2, 2.7 | 0 | SiO2_Palik_Lossless | SiO2 |
| 3 | 'M2_router'**0.3 | 2.2, 3.3 | 0 | SiO2_Palik_Lossless | SiO2 |
| 4 | 'M1_heater' | 2.2, 2.4 | 0 | W_Werner2009 | LossyMetalMedium……(frequency_range=(100000000.0, 200000000000.0), conductivity=1.6, fit_param={'max_num_poles': 16}) |
| 5 | 'M2_router' | 2.4, 3 | 0 | Au_Olmon2012evaporated | LossyMetalMedium……(frequency_range=(100000000.0, 200000000000.0), conductivity=17.0, fit_param={'max_num_poles': 16}) |
| 6 | 'M_Open' | 3, 3.3 | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
| 7 | 'Oxide open to BOX' | 0, inf | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
| 8 | 'Si' | 0, 0.22 | 0 | cSi_Li1993_293K | Si |
| 9 | 'Si Slab' | 0, 0.09 | 0 | cSi_Li1993_293K | Si |
| 10 | 'Deep Trench' +…… 'Thermal Isolation Trenches' | -inf, inf | 0 | Medium(permittivity=1.0) | Medium(permittivity=1.0) |
Ports
| Name | Classification | Description | Width (μm) | Limits (μm) | Radius (μm) | Modes | Target n_eff | Path profiles (μm) | Voltage path | Current path |
|---|---|---|---|---|---|---|---|---|---|---|
| MM_TE_1550_2000 | optical | Multimode Strip TE 1550 nm,…… w=2000 nm | 6 | -2, 2.22 | 0 | 10 | 3.5 | 'Si': 2 | ||
| MM_TE_1550_3000 | optical | Multimode Strip TE 1550 nm,…… w=3000 nm | 6 | -2, 2.22 | 0 | 15 | 3.5 | 'Si': 3 | ||
| Rib_TE_1310_350 | optical | Rib (90 nm slab) TE 1310 nm,…… w=350 nm | 2.35 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35, 'Si…… Slab': 3 | ||
| Rib_TE_1550_500 | optical | Rib (90 nm slab) TE 1550 nm,…… w=500 nm | 2.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5, 'Si…… Slab': 3 | ||
| Slot_TE_1550_500 | optical | Slot TE 1550 nm, w=500 nm,…… gap=100nm | 3 | -1, 1.22 | 0 | 1 | 3.5 | 'Si': 0.2 (-0.15),…… 'Si': 0.2 (+0.15) | ||
| TE-TM_1550_450 | optical | Strip TE-TM 1550, w=450 nm | 2.2 | -1, 1.22 | 0 | 2 | 3.5 | 'Si': 0.45 | ||
| TE_1310_350 | optical | Strip TE 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.35 | ||
| TE_1310_410 | optical | Strip TE 1310 nm, w=410 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.41 | ||
| TE_1550_500 | optical | Strip TE 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 | 3.5 | 'Si': 0.5 | ||
| TM_1310_350 | optical | Strip TM 1310 nm, w=350 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.35 | ||
| TM_1550_500 | optical | Strip TM 1550 nm, w=500 nm | 1.5 | -0.6, 0.82 | 0 | 1 + 1 (TM) | 3.5 | 'Si': 0.5 | ||
| eskid_TE_1550 | optical | eskid TE 1550 | 2 | -0.7, 0.92 | 0 | 1 | 3.5 | 'Si': 0.35,…… 'Si': 0.06 (+0.265), 'Si': 0.06 (-0.265), 'Si': 0.06 (+0.385), 'Si': 0.06 (-0.385), 'Si': 0.06 (+0.505), 'Si': 0.06 (-0.505), 'Si': 0.06 (+0.625), 'Si': 0.06 (-0.625) |
Background medium
- Optical: Medium(permittivity=1.0)
- Electrical: Medium(permittivity=1.0)
Connections: []
[4]:
technology.random_variables
[4]:
[RandomVariable('si_thickness', **{'value': 0.22, 'stdev': 0.0037166666666666667})]
Step 2: Loading foundry provided PDK components¶
[5]:
cross = siepic_pdk.component("ebeam_crossing4")
cross
[5]:
[6]:
cross.models
[6]:
{'Tidy3D': Tidy3DModel(run_time=None, medium=None, symmetry=(0, 0, 0), boundary_spec=None, monitors=(), structures=(), grid_spec=None, shutoff=None, subpixel=None, courant=None, port_symmetries=[('P0', 'P1', {'P1': 'P0', 'P2': 'P3', 'P3': 'P2'}), ('P0', 'P2', {'P1': 'P3', 'P2': 'P1', 'P3': 'P0'}), ('P0', 'P3', {'P1': 'P2', 'P2': 'P0', 'P3': 'P1'})], bounds=((None, None, None), (None, None, None)), source_gap=None, simulation_updates=None, verbose=True)}
Step 3: Covert 2D layout files to 3D for electromagnetic simulations¶
[7]:
# run 3D fdtd simulation to compute s_matrix
wavelengths = np.linspace(1.535, 1.565, 20)
s_matrix = cross.s_matrix(frequencies = pf.C_0/wavelengths)
Starting…
07:33:05 -03 Loading simulation from local cache. View cached task using web UI at 'https://tidy3d.simulation.cloud/workbench?taskId=fdve-2c06298b-e23 d-4f3b-aa6c-b7741eb8334d'.
Progress: 100%
[8]:
plt = pf.plot_s_matrix(s_matrix, y="dB", input_ports= ["P0"], output_ports = ["P1"])
