Layout Verification

Design rule checks and layout-versus-schematic comparisons run through an external engine selected by the engine argument: KLayout (DRC and LVS) or Calibre (DRC). KLayout 0.29.12 or newer is required; each check stops with an error naming an older version.

With engine="calibre", the rules file is an SVRF rule deck. Calibre runs a copy of it whose LAYOUT PATH, LAYOUT SYSTEM, LAYOUT PRIMARY (when the source is a component), DRC RESULTS DATABASE and DRC SUMMARY REPORT (when the deck declares one) name the files of the check; the deck itself is never edited. args holds Calibre’s command-line arguments, such as ("-hier", "-turbo", "4"). The Calibre engine requires a Photonic Canvas (PhotonForge Enterprise) license. Both engines return the same verification.DRCResults.

The LVS schematic can come from the component itself: with schematic unset or set to a Component, lvs_check writes a SPICE schematic from Component.get_netlist. Routes built by the parametric routing functions are written as wires and virtual connections as nets, so a routed component is its own design intent, and so is its unrouted version. pre_export_function adds the port markers and labels the rules file extracts pins from.

Functions

• photonforge.drc_check Run a design rule check (DRC) on a layout.
• photonforge.lvs_check Run a layout-versus-schematic (LVS) comparison.
• photonforge.load_drc_results Read the results database of an earlier design rule check.
• photonforge.load_lvs_results Read the results database of an earlier layout-versus-schematic

DRC Results

Coordinates are in micrometers. DRCResults is also available as photonforge.DRCResults.

• photonforge.DRCResults Results of a DRC run, from any engine.
• photonforge.verification.DRCViolation The markers of one rule (category).
• photonforge.verification.DRCCell A cell of the results.
• photonforge.verification.DRCCellReference An example placement of a cell in another cell; parent is that cell’s key.
• photonforge.verification.Placement Magnification, then mirroring about x, then counter-clockwise rotation, then displacement.
• photonforge.verification.DRCMarker Marker of one violation, with the cell it was found in.
• photonforge.verification.EdgeMarker One edge, for rules that report edges.
• photonforge.verification.EdgePairMarker Two edges; symmetric for same-layer rules (width, space), directed otherwise,
• photonforge.verification.PolygonMarker A polygon with optional holes; boxes and paths are reported as polygons.
• photonforge.verification.TextMarker A text output and its position.
• photonforge.verification.ValueMarker Any other marker value, as the engine prints it (KLayout only).

Layout Pins

A photonic runset tells the ports of a passive cell apart only by layout labels, which the layout export does not write. layout_pins returns a pre_export_function for lvs_check that draws them on the layers the runset reads: devices get their core shapes as an outline, a box at each port and the port name; circuits get the names; routes nothing.

• photonforge.verification.layout_pins Pre-export function that draws pins over Port.

LVS Results

LVSResults is also available as photonforge.LVSResults.

• photonforge.LVSResults Results of a KLayout LVS run.
• photonforge.verification.LVSComparison The comparison of a layout circuit with a schematic circuit.
• photonforge.verification.LVSPair Two objects KLayout paired; either side is None when it found no partner.
• photonforge.verification.LVSMessage A comparison or extraction message.
• photonforge.verification.LVSGeometry A polygon attached to a message.
• photonforge.verification.LVSNetlist The layout or the schematic netlist; circuits is in file order, children first.
• photonforge.verification.LVSCircuit A circuit of a netlist, with lookups by id or index that raise KeyError.
• photonforge.verification.LVSNet A net of a circuit, with its connections and, for the layout, its geometry per layer.
• photonforge.verification.LVSConnection What a net connects to: a circuit pin, a subcircuit pin, or a device terminal.
• photonforge.verification.LVSLabel A text label KLayout attached to a layout net.
• photonforge.verification.LVSPin A circuit pin and the net it connects to.
• photonforge.verification.LVSDevice An extracted or schematic device; terminals maps terminal names to net ids.
• photonforge.verification.LVSDevicePart One of the extracted devices combined into a device.
• photonforge.verification.LVSDeviceClass A device class; template names KLayout’s built-in class it derives from.
• photonforge.verification.LVSParameterDefinition A parameter of a device class; primary parameters are compared by LVS.
• photonforge.verification.LVSDeviceAbstract The geometry of an extracted device, per terminal and layer.
• photonforge.verification.LVSSubcircuit An instance of another circuit; pins maps its pin indices to net ids.
• photonforge.verification.LVSLayer A layer of the extraction and the layers and global nets it connects to.