verification.layout_pins

layout_pins(
    design: photonforge.Component,
    core_layer: tuple[int, int],
    *,
    outline_layer: tuple[int, int] | None,
    label_layer: tuple[int, int] | None,
    pin_layer: tuple[int, int] | None,
    pin_length: float = 0.1,
) -> collections.abc.Callable[[photonforge.Component], None]

Pre-export function that draws pins over Port.

The exported cells of design are marked by their place in its hierarchy:

• A device, a cell whose references carry no ports or terminals, gets its shapes on core_layer, at every depth, copied to outline_layer, so that the runset can keep its waveguide from joining its ports; a box on pin_layer straddling each planar port, as wide as the port’s core profile; and the port name on label_layer at the port center.
• A circuit, a cell with references to cells with ports, gets the port names, and a box at each port of its references: a port no instance connects is then a pin too, and a connection the intent draws to it is reported.
• A route from parametric, and the sections inside it, get nothing: routes are wires in the derived schematic, and the runset’s align flattens them.

Fiber and Gaussian ports have no layout, and a port whose spec has no profile on core_layer, such as an electrical port, is not one the runset connects: neither is marked. A core_layer no port of design uses is refused, since nothing would be drawn. These layers and shapes are one convention; a runset that reads another takes a function of your own, for which this one is a template.

Args

• design: Component to be checked. Its hierarchy decides which cells are devices and which are circuits.
• core_layer: Waveguide core layer, which the runset connects.
• outline_layer: Layer of the device outlines, or None for none.
• label_layer: Layer of the port names, or None for none.
• pin_layer: Layer of the port boxes, or None for none.
• pin_length: Length of the pin boxes, along the port direction.

Returns

Function for pre_export_function of lvs_check.