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lvs_check

lvs_check(
    source,
    rules,
    *,
    schematic=None,
    engine=None,
    args=None,
    variable_names=None,
    results_file=None,
    load_shapes=True,
    timeout=None,
    pre_export_function=None,
    top_level=None,
    schematic_top_level=None,
    show_progress=True,
)

Run a layout-versus-schematic (LVS) comparison.

For KLayout, the rules file is an LVS runset (.lvs or .lylvs) that receives the layout, schematic and results paths as script variables and calls source($gdsfile), schematic($schematicfile), report_lvs($resultsfile) and compare. The results database is then read with KLayout’s own Python module, so the executable must include Python, as the official builds do.

For Calibre, the rules file is an SVRF rule deck. Calibre runs a copy of it whose LAYOUT PATH, LAYOUT SYSTEM, LAYOUT PRIMARY, SOURCE PATH, SOURCE SYSTEM (for a schematic written from a component), SOURCE PRIMARY, LVS REPORT and MASK SVDB DIRECTORY name the files and cells of this check; the deck itself is never edited. The run is flat (-flatten) unless args holds -hier. The report, the extraction report and the discrepancy file of the results database are read in compiled code.

Args

  • source (Component | str | PathLike): Component to check, exported to GDSII with default settings, or path to a GDSII or OASIS file.
  • rules (str | PathLike): Rules file for the engine.
  • schematic (Component | str | PathLike | None): Design intent. A component is written as a SPICE schematic from its netlist (see note); None uses source, which must then be a component. A path is a netlist in a format the rules file reads, usually SPICE.
  • engine (str | None): Verification engine, "klayout" or "calibre". None uses config.default_drc_lvs_engine, and when that is unset the first engine found (KLayout, then Calibre).
  • args (dict[str, object] | Sequence[str] | None): For KLayout, extra script variables for the rules file, passed as -rd name=value with str(value). For Calibre, extra command-line arguments, one per item, such as ("-hier", "-turbo", "4").
  • variable_names (dict[str, str] | None): Names of the file variables used by a KLayout runset when they differ from the defaults. Keys are "gdsfile", "schematicfile" and "resultsfile".
  • results_file (str | PathLike | None): Keep the engine’s native results at this path: KLayout’s .lvsdb, or a directory receiving Calibre’s report, extraction report, extracted netlist and results database.
  • load_shapes (bool): Include the layout geometry of each net (KLayout only; Calibre reports no geometry).
  • timeout (float | None): Seconds allowed for each engine run; TimeoutError when one exceeds it.
  • pre_export_function (Callable[[Component], object] | None): Called with a shallow copy of each component exported from source or written for schematic, as in write_layout. Use it to add the port markers and labels the rules file extracts pins from; verification.layout_pins can be used as an example.
  • top_level (str | None): Layout cell Calibre compares (its LAYOUT PRIMARY). None uses the component’s name when source is a component, otherwise the deck’s own primary. Calibre only.
  • schematic_top_level (str | None): Schematic cell Calibre compares it with (its SOURCE PRIMARY). None uses the written schematic’s cell when schematic is a component or None, otherwise the deck’s own, or the layout cell’s name. Calibre only.
  • show_progress (bool): Show the phase and the elapsed time while the engine runs.

Returns

verification.LVSResults: Verdict, circuit comparisons, and both netlists (Calibre’s hold the objects its discrepancies name). Differences never raise: a KLayout runset that exits with a non-zero code on a mismatch does not raise once compare ran, and a Calibre run that compared, or aborted on a supply error, is a result; the code is in LVSResults.exit_code. A KLayout runset that stops before compare writes no results and raises.

Note

A schematic written from a component has one subcircuit per cell, named as in the exported layout, whose pins are its planar ports, then its terminals; fiber and Gaussian ports have no layout. Each instance with pins is the line X<i>, where i is its index in Component.get_netlist, and the results carry its placement. Connections, butt couplings, virtual connections, terminal nets and virtual nets become nets. A route built by parametric.route, parametric.route_auto and the other route_* functions is a wire: its ports are one net, and neither it nor its sections are written, so a routed component is its own design intent. Port terminals and mode counts are not represented.

KLayout is taken from config.klayout_executable when set, then searched in PATH and in common install locations. Calibre is taken from config.calibre_executable when set, then searched in PATH, $CALIBRE_HOME/bin and $MGC_HOME/bin, and requires a PhotonForge Photonic Canvas license.