verification
DRCCell
Section titled “DRCCell”photonforge.verification.DRCCell A cell of the results.
DRCCellReference
Section titled “DRCCellReference”photonforge.verification.DRCCellReference An example placement of a cell in another cell; parent is that cell’s key.
DRCMarker
Section titled “DRCMarker”photonforge.verification.DRCMarker Marker of one violation, with the cell it was found in.
DRCViolation
Section titled “DRCViolation”photonforge.verification.DRCViolation The markers of one rule (category).
photonforge.verification.Edge Built-in immutable sequence.
EdgeMarker
Section titled “EdgeMarker”photonforge.verification.EdgeMarker One edge, for rules that report edges.
EdgePairMarker
Section titled “EdgePairMarker”photonforge.verification.EdgePairMarker Two edges; symmetric for same-layer rules (width, space), directed otherwise,
LVSCircuit
Section titled “LVSCircuit”photonforge.verification.LVSCircuit A circuit of a netlist, with lookups by id or index that raise KeyError.
LVSComparison
Section titled “LVSComparison”photonforge.verification.LVSComparison The comparison of a layout circuit with a schematic circuit.
LVSConnection
Section titled “LVSConnection”photonforge.verification.LVSConnection What a net connects to: a circuit pin, a subcircuit pin, or a device terminal.
LVSDevice
Section titled “LVSDevice”photonforge.verification.LVSDevice An extracted or schematic device; terminals maps terminal names to net ids.
LVSDeviceAbstract
Section titled “LVSDeviceAbstract”photonforge.verification.LVSDeviceAbstract The geometry of an extracted device, per terminal and layer.
LVSDeviceClass
Section titled “LVSDeviceClass”photonforge.verification.LVSDeviceClass A device class; template names KLayout’s built-in class it derives from.
LVSDevicePart
Section titled “LVSDevicePart”photonforge.verification.LVSDevicePart One of the extracted devices combined into a device.
LVSGeometry
Section titled “LVSGeometry”photonforge.verification.LVSGeometry A polygon attached to a message.
LVSLabel
Section titled “LVSLabel”photonforge.verification.LVSLabel A text label KLayout attached to a layout net.
LVSLayer
Section titled “LVSLayer”photonforge.verification.LVSLayer A layer of the extraction and the layers and global nets it connects to.
LVSMessage
Section titled “LVSMessage”photonforge.verification.LVSMessage A comparison or extraction message.
LVSNet
Section titled “LVSNet”photonforge.verification.LVSNet A net of a circuit, with its connections and, for the layout, its geometry per layer.
LVSNetlist
Section titled “LVSNetlist”photonforge.verification.LVSNetlist The layout or the schematic netlist; circuits is in file order, children first.
LVSPair
Section titled “LVSPair”photonforge.verification.LVSPair Two objects KLayout paired; either side is None when it found no partner.
LVSParameterDefinition
Section titled “LVSParameterDefinition”photonforge.verification.LVSParameterDefinition A parameter of a device class; primary parameters are compared by LVS.
LVSPin
Section titled “LVSPin”photonforge.verification.LVSPin A circuit pin and the net it connects to.
LVSSeverity
Section titled “LVSSeverity”photonforge.verification.LVSSeverity
LVSStatus
Section titled “LVSStatus”photonforge.verification.LVSStatus
LVSSubcircuit
Section titled “LVSSubcircuit”photonforge.verification.LVSSubcircuit An instance of another circuit; pins maps its pin indices to net ids.
LVSVerdict
Section titled “LVSVerdict”photonforge.verification.LVSVerdict
Placement
Section titled “Placement”photonforge.verification.Placement Magnification, then mirroring about x, then counter-clockwise rotation, then displacement.
photonforge.verification.Point Built-in immutable sequence.
Polygon
Section titled “Polygon”photonforge.verification.Polygon Built-in immutable sequence.
PolygonMarker
Section titled “PolygonMarker”photonforge.verification.PolygonMarker A polygon with optional holes; boxes and paths are reported as polygons.
TextMarker
Section titled “TextMarker”photonforge.verification.TextMarker A text output and its position.
ValueMarker
Section titled “ValueMarker”photonforge.verification.ValueMarker Any other marker value, as the engine prints it (KLayout only).
layout_pins
Section titled “layout_pins”photonforge.verification.layout_pins Pre-export function that draws pins over Port.