# Layout-versus-schematic runset for the LiDAR chip, for KLayout. PhotonForge passes the exported
# layout, the schematic it writes from the nets declared on the chip, and the results path.
source($gdsfile)
schematic($schematicfile)
report_lvs($resultsfile)

# Hierarchical extraction: every cell is compared with its own subcircuit
deep

# The layers that conduct: the routing metal, the vias onto the heaters, the plugs on silicon and
# on germanium. The heater film (12, 0), the silicon and the germanium are left out: a heater is a
# resistor between its two vias and a photodiode a device between its two plugs, so each shows as
# two separate pins, and a trace bridging a heater's ends merges two declared nets into one.
m1 = input(14, 0)
via = input(13, 0)
contact = input(10, 0)
ge_contact = input(11, 0)

# The terminal names, written as text labels on the metal before export, name the nets
m1_labels = labels(14, 0)

connect(m1, via)
connect(m1, contact)
connect(m1, ge_contact)
connect(m1, m1_labels)

netlist
align
compare